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| CY7C1019DV33 1-Mbit (128K x 8) Static RAM Features * Pin- and function-compatible with CY7C1019CV33 * High speed -- tAA = 10 ns * Low Active Power -- ICC = 60 mA @ 10 ns * Low CMOS Standby Power * * * * * * -- ISB2 = 3 mA 2.0V Data retention Automatic power-down when deselected CMOS for optimum speed/power Center power/ground pinout Easy memory expansion with CE and OE options Available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages Functional Description[1] The CY7C1019DV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1019DV33 is available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages. Logic Block Diagram INPUTBUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 CE WE OE A9 A10 A11 A12 A13 A14 A15 A16 ROW DECODER I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5 128K x 8 ARRAY COLUMN DECODER POWER DOWN I/O6 I/O7 Note 1. For guidelines on SRAM system design, please refer to the `System Design Guidelines' Cypress application note, available on the internet at www.cypress.com Cypress Semiconductor Corporation Document #: 38-05481 Rev. *D * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised November 8, 2006 [+] Feedback CY7C1019DV33 Selection Guide -10 (Industrial) Maximum Access Time Maximum Operating Current Maximum Standby Current 10 60 3 Unit ns mA mA Pin Configurations[2] 48-ball VFBGA (Top View) 1 NC I/O0 I/O1 VSS VCC I/O2 I/O3 NC 2 OE NC NC NC NC NC NC A10 3 A2 A1 A0 NC NC A14 A15 A16 4 A6 A5 A4 A3 NC A11 A12 A13 5 A7 CE NC NC NC I/O4 WE A9 6 NC I/O7 I/O6 VCC VSS I/O5 A8 NC A B C D E F G H A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 SOJ/TSOPII Top View 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 Note 2. NC pins are not connected on the die. Document #: 38-05481 Rev. *D Page 2 of 11 [+] Feedback CY7C1019DV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VCC to Relative GND[3] ... -0.3V to + 4.6V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.3V to VCC + 0.3V DC Input Voltage[3] ................................ -0.3V to VCC + 0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Range Industrial Ambient Temperature -40C to +85C VCC 3.3V 0.3V Speed 10 ns Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] GND < VI < VCC GND < VI < VCC, Output Disabled 100MHz 83MHz 66MHz 40MHz ISB1 ISB2 Automatic CE Power-down Current--TTL Inputs Automatic CE Power-down Current--CMOS Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.0 -0.3 -1 -1 -10 (Industrial) Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 60 55 45 30 10 3 Max. Unit V V V V A A mA mA mA mA mA mA Input Leakage Current Output Leakage Current VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Note 3. VIL (min.) = -2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. Document #: 38-05481 Rev. *D Page 3 of 11 [+] Feedback CY7C1019DV33 Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF Thermal Resistance[4] Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, four-layer printed circuit board SOJ 56.29 38.14 TSOP II VFBGA 62.22 21.43 36 9 Unit C/W C/W AC Test Loads and Waveforms[5] ALL INPUT PULSES 90% 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V Rise Time: 1 V/ns Z = 50 OUTPUT 3.0V GND 10% 90% 10% 30 pF* (a) (b) Fall Time: 1 V/ns High-Z characteristics: R1 317 3.3V OUTPUT 5 pF R2 351 (c) Notes 4. Tested initially and after any design or process changes that may affect these parameters. 5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05481 Rev. *D Page 4 of 11 [+] Feedback CY7C1019DV33 Switching Characteristics Over the Operating Range [6] Parameter Read Cycle tpower[7] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[10] tPD[10] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE LOW to Low Z[8, 9] 3 5 0 10 Z[8, 9] Z[9] 0 5 3 10 5 100 10 10 s ns ns ns ns ns ns ns ns ns ns ns Description -10 (Industrial) Min. Max. Unit CE HIGH to High CE LOW to Power-Up CE HIGH to Power-Down Write Cycle[11, 12] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z WE LOW to High [9] 10 8 8 0 0 7 5 0 3 5 ns ns ns ns ns ns ns ns ns ns Z[8, 9] Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 7. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. This parameter is guaranteed by design and is not tested. 11. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05481 Rev. *D Page 5 of 11 [+] Feedback CY7C1019DV33 Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR [4] tR[13] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 0 tRC Conditions Min. 2.0 3 Max. Unit V mA ns ns Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[14, 15] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[15, 16] ADDRESS tRC CE tACE OE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE Notes 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for Read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document #: 38-05481 Rev. *D Page 6 of 11 [+] Feedback CY7C1019DV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[17, 18] tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[17, 18] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 19 tHZOE DATAIN VALID tHD Notes 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05481 Rev. *D Page 7 of 11 [+] Feedback CY7C1019DV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[12, 18] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 19 tHZWE DATA VALID tLZWE tHD tPWE tHA Truth Table CE H L L L OE X L X H WE X H L H High Z Data Out Data In High Z I/O0-I/O7 Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1019DV33-10VXI CY7C1019DV33-10ZSXI CY7C1019DV33-10BVXI Package Diagram 51-85033 51-85095 51-85150 Package Type 32-pin (400-Mil) Molded SOJ (Pb-free) 32-pin TSOP Type II (Pb-free) 48-ball VFBGA (Pb-free) Operating Range Industrial Please contact your local Cypress sales representative for availability of these parts. Document #: 38-05481 Rev. *D Page 8 of 11 [+] Feedback CY7C1019DV33 Package Diagrams Figure 1. 32-pin (400-Mil) Molded SOJ (51-85033) 51-85033-A 51-85033-*B Figure 2. 32-pin Thin Small Outline Package Type II (51-85095) 51-85095-** Document #: 38-05481 Rev. *D Page 9 of 11 [+] Feedback CY7C1019DV33 Package Diagrams (continued) Figure 3. 48-ball VFBGA (6 x 8 x 1 mm) (51-85150) TOP VIEW BOTTOM VIEW A1 CORNER O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A B C 8.000.10 8.000.10 0.75 5.25 D E F G H A B C D E 2.625 F G H A B 6.000.10 A 1.875 0.75 3.75 B 6.000.10 0.55 MAX. 0.25 C 0.15(4X) 0.210.05 0.10 C 51-85150-*D SEATING PLANE 0.26 MAX. C 1.00 MAX All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05481 Rev. *D Page 10 of 11 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1019DV33 Document History Page Document Title: CY7C1019DV33, 1-Mbit (128K x 8) Static RAM Document Number: 38-05481 REV. ** *A *B ECN NO. 201560 233750 262950 Issue Date See ECN See ECN See ECN Orig. of Change SWI RKF RKF Description of Change Advance Information data sheet for C9 IPP DC parameters modified as per EROS (Spec # 01-02165 Rev *A) Pb-free Offering in Ordering Information Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information Reduced Speed bins to -8 and -10 ns Converted from Preliminary to Final Removed Commercial Operating range Removed 8 ns speed bin Added ICC values for the frequencies 83MHz, 66MHz and 40MHz Added 48-ball VFBGA package Updated Thermal Resistance table Updated Ordering Information table Changed Overshoot spec from VCC+2V to VCC+1V in footnote #3 *C *D 307598 520652 See ECN See ECN RKF VKN Document #: 38-05481 Rev. *D Page 11 of 11 [+] Feedback |
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